How the Type G Gate Worked

apollo 3 input NOR gate
An image of the silicon die inside the Type G 3 input NOR gate used to power the Apollo Guidance computer.

Previously I went through the three input NOR gate that ran the Apollo Guidance Computer and how the circuit works. Previous to that I also told the story of how this chip partially funded Silicon Valley as we know it today. This post builds on that and goes through how the silicon works, and the simplicity of the circuit. Quite a famous image of the chip, fairly detailed image of the silicon inside the device spurred on this post, and taught me lots about silicon that I want to pass on.

apollo 3 input NOR gate schem annotated
The schematic of the 3 input NOR gate. From the schematic of the Apollo Guidance Computer. Annotated with my own designators for reference.

The above schematic of the 3 input NOR gate is also shown in previous posts. It is from the NASA Apollo Guidance Computer schematic, but I have annotated it so that I can reference to specific parts. It is a handy schematic considering it was right at the start of the development of semiconductors. The first image in the post is the best image of the silicon, but is not very big. The biggest image I can find is not quite as sharp, but is much better to annotate, it is the same chip. The first annotation shows the pinout of the device, and how those pins actually connect to the pins.

apollo 3 input NOR pin out
The silicon of the 3 input NOR gate with annotations to show which pin is connected. The pin numbers are from the schematic.
Showing how pins are connected
An image showing how the pins coming off of the silicon are connected into pins of the flat pack.

The noted parts of the above images are pins 5 and 10, and are the starting points to deciphering the layout. If you look at pin 5 and 10 on the schematic, they correspond to GND and power respectively. They are the only pins that are shared between both NOR gates. Apart from that the two sides look remarkably similar, and are basically a mirrored version. To figure which is ground and which is power, the resistors need to be taken into account.

apollo 3 input NOR gate resistors
The resistors on the silicon of the device. Shown above as brown lines they are P doped silicon that act like a resistor.

The above image shows the resistors found on the device. They tend to just be a thin section of P doped silicon, and above connect two sections of aluminum to form a resistor. It is also noted that there is big section of brown surrounding the whole circuit. Although it functions like a resistor and is made in the same way, it is puterly for ESD purposes, protecting the circuit. This big ring also is a big hint that it is connected to ground (pin 5). the second hint is that GND has no resistors attached to it on the schematic, but power has two. They are R1 and R2, connecting to pin 9 and 1 respectively, and are pull up resistors. Pin R3 to R8 are simply the base resistors for the transistors. They are all roughly the same size, and are there are 6 of them. The transistors are also fairly obvious in the centre of the silicon.

apollo NOR gate transistors
The centre silicon from the Apollo 3 input NOR gate. The transistors have been shown, and the collector, base and emitter also shown,

The above image is showing the heart of the device. the 6 transistors that make it resistor-transistor logic. As you can see in the above image, all the collectors are connected together, connected to pins 1 and 9. If you look closely, the base and emitter of each transistor sit inside a brown section like the resistors. This is P doped silicon and forms the base-emitter junction. This allows the base and emitter to sit anywhere within that P doped silicon detection to work. This means that the transistors do not conform to the standard Collector-base-emitter topology. All of the emitters are also connected together via the aluminium placed on the top, but the P doped sections of each device are seperate. As all the transistors of each device have common emitters, it doesn’t matter that they are all connected together, by design, only one of the transistors needs to be on for it to function.

Ken Shirriff transistor side view
A great image showing how the transistor works from a side view by Ken Shirriff.

The above image found on Ken Shirriff’s blog shows how the transistor works with the emitter and base in the P doped silicon. I may do some more posts about it, but his blog is a great place to find more information on silicon reverse engineering.

Electronics world 1963
A cutout from electronics world in 1963 showing the new process of planar technology. This method was used to make the NOR gate.

The above image is an interesting one I found while researching this chip. A section in electronics world 1963 showing how micrologic is made. The type G chip was part of the second batch of micrologic circuits. This section was useful to see how silicon was actually manufactured, and in some ways, still is today.

The NOR Gate That Got Us To The Moon

Type G micrologic
The Fairchild Type ‘G’ Micrologic gate for the Apollo Guidance Computer – this is the flat pack verison

In a previous post I talked about how the going to the moon kick started the silicon age. If you haven’t read it, it is short but really interesting story about how NASA made Integrated circuits cheap, and partially funded what we now know as Silicon Valley. In this post I am going to take a slightly closer look at the circuit that ran the famous type “G” Micrologic gate that ran the Apollo Guidance Computer.

apollo 3 input NOR gate
The official NASA schematic of the Type G micrologic gate found in the Apollo Guidance Computer

As you can see in the above image, the circuit was not particularly complicated. You have to remember that this is very early logic, before CMOS or NMOS or any other fancy IC technologies. This is basically two 3 input NOR gates, they both run off the same power, with pin 10 at the top, and the negative which was likely ground being shared on pin 5. The output for the left NOR gate is pin 1, and the output for the right is pin 9. The three inputs for the left are pins 4, 2 and 3, with the right having pins 6, 7, and 8 as inputs. Simply put, the output is “pulled” high to power when all the inputs are OFF. The resistor between pin 10 and pin 1 (or 10 and 9) are a simple pull up resistor as you would find in most electronic circuits. As expected with a NOR gate, the output will be only be ON when all the inputs are OFF. When any of the inputs are ON the output of that gate will be pulled to ground. One two, or all the inputs can be on, but it just needs one to turn OFF the output. The resistors going into the base of the transistor are just to limit the current.

3 input NOR
My breadboarded version of the 3 input NOR gate, it is made with BC547 transistors and a DIP switch. the output has been inverted with the LED.

I made a simple recreation of this circuit using BC547 NPN transistors, but most NPN transistors would work, these were ones I found in my parts box. As you can see in the image above, I have made it on a breadboard, with the inputs being a DIP switch attached to the power (5V in this case). The base resistors for the transistors are 1K and the pull-up to 5V is a 10K. I recommend making up this circuit if you want to learn a bit more about logic, and is a cheaper method than going out to buy 74 series logic chips! As you can see in the images there are a number of states that I showed the circuit in, and notice that if any of the switches are on, the circuit turns on, this is slightly against what I mentioned earlier, but thats due to the output LED using the transistor as a current sink, not a source, so the output is inverted. Basically, when the output is 0 the LED turns on. The only time the LED is off (output high) is when no switches are on, meaning all the transistors are off.

apollo 3 input NOR gate
An image of the silicon die inside the Type G 3 input NOR gate. We will be going through how the layout works in a future post.

The final point for this post is why the circuit is actually quite inefficient. Modern logic is amazingly low power compared to this. One of the biggest issues is that it is always taking power in some way. When the inputs are off, there is still some leakage through the pull up resistor, when an input is on, then there is current going through the resistor to ground. Also, by the nature of the transistors there is always parasitic leakages, and inefficiencies in the process. They are only small numbers, but the AGC used over 3000 of these circuits, so the small leakages soon add up to draw some hefty power needs, especially for battery powered operations.

If you enjoyed this post, take a look at the rest of my blog, there is lots about space, electronics and random history. I am always open to ideas and feedback, and where is best to post links to my posts.

How Going To The Moon Kick-started the Silicon Age

In the late 1950’s, there were three people who were at the epicenter of a huge breakthrough in the world of electronics, the invention of the Integrated Circuit (IC). Jack Kilby of Texas Instruments, Kurt Lehovec of Sprague Electric Company, and Robert Noyce of Fairchild Semiconductor. In August 1959, Fairchild Semiconductor Director of R&D, Robert Noyce asked Jay Last to begin development on the first Integrated Circuit. They developed a flip-flop with four transistors and five resistors using a modified Direct Coupled Transistor Logic. Named the type “F” Flip-Flop, the die was etched to fit into a round TO-18 packaged, previously used for transistors. Under the name Micrologic, the “F” type was announced to the public in March 1961 via a press conference in New York and a photograph in LIFE magazine. Then in October, 5 new circuits were released, the type “G” gate function, a half adder, and a half shift register.

The Type F flip flop
Junction-isolated version of the type “F” flip-flop. The die were etched to fit into a round TO-18 transistor package
Type F life image
Physically-isolated Micrologic flip-flop compared to a dime from LIFE magazine March 10, 1961

These first few integrated circuits were relatively slow, and only replaced a handful of components, while being sold for many times the price of a discrete transistor. The only applications that could afford the high prices were Aerospace and Military systems. The low power consumption and small size outweighed the price drawbacks, and allowed for new and more complex designs. In 1961, Jack Kilby’s colleague Harvey Craygon built a “molecular electronic computer” as a demonstration for the US Air Force to show that 587 Texas Instruments IC’s could replace 8,500 discrete components (like transistors and resistors) that performed the same function. In 1961, the most significant use of Fairchild Micrologic devices were in the Apollo Guidance Computer (AGC). It was designed by MIT and used 4,000 type “G” three input NOR gates. Over the Apollo project, over 200,000 units were purchased by NASA. The very early versions were $1000 each ($8000 today) but over the years prices fell to $20-$30 each. The AGC was the largest single user of IC’s through 1965.

apollo guidance computer logic module
Apollo logic module assembled by Raytheon to be used in the AGC
Type G micrologic
Philco Ford also produced the Fairchild Type ‘G’ Micrologic gate for the Apollo Guidance Computer – this is the flat pack verison

Note that although Fairchild designed and owned the type “G” device, they were mostly made by Raytheon and Philco Ford under licence from Fairchild. Over this time many semiconductor manufacturers such as Texas Instruments, Raytheon and Philco Ford were also making large scale silicon production for other military equipment. These included the LGM-30 Minuteman ballistic missiles, and a series of chips for space satellites. This major investment from the government and the military kick started the development of the increasingly complex semiconductor, and eventually forced the prices low enough for non military applications. The processes improved and by the end of the Apollo program, hundreds of transistors could be fitted into an IC, and more complex circuits were being made. Eventually the costs of adding more transistors to a circuit got extremely low, with the difficulty being the quality of manufacturing. It could be argued that NASA and the Pentagon paved the way for silicon device production as we know it today.

Four Bit Carry Adder/Subtractor Circuit

After creating my 1 bit full adder design found in a previous post, I decided to go for something a little more complicated. I wanted to prove to myself that the ripple carry system worked, so the obvious choice is to make a multi bit device. 4 bits seemed like a good amount, it’s a value used in some early ALU’s so it can be used in a future project. To make it more interesting I added in the ability to make the device a Subtractor at the same time. When you look at the schematic, it only requires one more device per adder, so it’s not even an expensive thing to implement, but adds lots of functionality. As with the 1 bit adder, I have attempted to build this adder using only single logic chips.

4 bit adder-subtractor circuit

The first stage is to know the logic circuit, its widely known and can be found pretty easily all over the web. I’m not going to explain how it’s created (I can always make a separate post on that) but I can describe how to use it. The aim is for the device to take two 4 bit inputs (0 – 15), along with a carry from another adder. So the adder needs to be able to output a value between 0 and 31. In binary this can be shown as 5 bits, so we have 2 outputs. This the S output is a 4 bit bus, and the Co output bumps this up to the 5 bits we need to make 31. A truth table can be made for this but it would be 32 lines long, so too much for this post. You could regard it as a personal challenge if you want to attempt it on your own.

So I got onto Altium and made a schematic of this circuit using some of the low voltage 7400 LVC series individual logic gates that I used on the previous adder I made. They come in SOT23-5 packages which are leaded a nice size to solder. Plus they are a size where it’s possible to probe the pins fairly easily. Luckily Altium shows the components as their logic symbols. Below I have shown the first two adders, the third and fourth are basically the same as the second one, which is the idea of the ripple carry adder.

The first two adders of the four found on the board

I also added a few LEDs to show what parts are on and off. This means the user can see the inputs and outputs. These LEDs run off the 5V input voltage, and have 220Ω current limiting resistors in series with them. Also, I have put in some 0.1 inch header pins so it can be attached into a breadboard and maybe even a micro.

The LEDs for the carry bits and outputs
The LEDs for the input bits

As a base of my circuit, I have decided on a double sided 100mm x 100mm board. This is quite big as you can see for the circuit I have made, but gives plenty of space for a soldering iron to get access. As well as this, it gives a nice amount of space for multimeter probes. I also tried to keep the individual logic chips in a similar arrangement as the schematic. This is meant to be used as a learning device, so it’s useful for the chips to line up with the diagram. The header pins for the inputs and outputs are placed on opposite sides of the board to make it more obvious for the user to see it. And the pins have designators written on the board so the user can see what each pin does. The input and output busses are placed in fairly logical places, and grouped together. There is no point having all the A inputs intertwined with the B inputs. The pins for the power and ground are on opposite sides with their own headers, only one needs to be connected for it to work. The LEDs that are directly attached to the pins are placed closer to the logic circuitry, but labeled clearly on the silkscreen. Most of the routing to the LEDs is on the underside of the board, else the top could get confusing. All the designators for components have been made half the normal size due to the small amount of parts used in the project. The below images show the PCB layout I created with the top copper being red, bottom copper being blue, and the silkscreen shown in yellow.

Top Copper

As you might be able to see, I have tried to keep all the power on the bottom side of the board. This leaves lots of space for the logic signals on the top, where the user is more likely to see. As you can see, most of the inputs and outputs of the circuit are also on the bottom side. This is because the way the busses work and input into the adder needs lots of crossing over and would add confusion into the design. This is why labels were used instead.

Bottom Copper

To make it easier to see, I made a larger image of the first and last adder in the series. As you can see, the only real difference in them is that the first has the add/subtract input shown by an LED, whereas the last shows the carry from the previous adder (C0). This is because the A/D bit is attached to all the adders, but the first bit doesn’t have a carry bit input. The carry on that adder is the input for the A/S. It serves the function of inverting the first bit, so that it works like 2’s complement when in subtract mode.

The layout of the first adder in the series
The layout of the last adder in the series

As noted above I used 7400 LVC series logic gates. The SOT23-5 package chips have the suffix of “BVD”. See the datasheets for each of the devices for more information. I have written a simple bill of materials below:

12x SN74LVC1G86DBVT – XOR gate
8x SN74LVC1G08DBVT – AND gate
4x SN74LVC1G32DBVT – OR gate
17x DO-214 LED’s
17x 0805 220Ω resistors
6x 5-pin 0.1″ header pins

The main downside to this type of adder is that is is very slow. Especially when you get to high bit amounts that you are trying to add. This adder will take at least 4 times as long as a single adder to add the two numbers together because the signal has to propage through 4 full adders. This problem is known as propagation delay, each logic chip will take a very short time to compute the output. Although this time is not perceivable by the human eye, if there are 100’s of logic gates in a row, then the delays start to add up and be a problem. If this circuit is to be used in a computer, it could need to make calculations thousands, or maybe millions of times a second, and a carry bit adder is not generally good at that. There are other, faster adders that I will show in a future post.

One Bit Adder Project

One thing that has always been interesting to me is using logic circuitry in electronics. It’s easy to implement something on a microcontroller in just a few lines of code, but the real challenge comes from making a boolean project using real logic gates. It’s something we all learn about if you have taken a basic computer science class, or even digital electronics. One of the first circuits you ever learn about is the adder. It’s pretty simple, teaches you how to cancel down boolean equations, and only has a few inputs and outputs. I have decided to try and make the circuit using real components, and see if I can get it to work.

full adder layout

The first stage is to know the logic circuit, its widely known and can be found pretty easily all over the web. I’m not going to explain how it’s created (I can always make a separate post on that) but I can describe how to use it. The aim is for the device to take two 1 bit inputs, along with a carry from another adder. So the adder needs to be able to output a value between 0 and 3. In binary this can be shown as 2 bits, so we have 2 outputs. The S output represents bit 1, and the Co output represents bit 2. Below is the truth table I used, if you want a little challenge, try and get the above circuit using boolean algebra.

A B Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

So I got onto Altium and made a schematic of this circuit using some of the low voltage 7400 LVC series individual logic gates. They come in SOT23-5 packages which are leaded and a nice size to solder. Plus they are a size where it’s possible to probe the pins fairly easily. Luckily Altium shows the components as their logic symbols.

1 bit adder 1 schematic

I also added a few LEDs to show what parts are on and off. This means the user can see the inputs and outputs. These LEDs run off the 5V input voltage, and have 220Ω current limiting resistors in series with them. Also, I have put in some 0.1 inch header pins so it can be attached into a breadboard and maybe even a micro.

1 bit adder 1 schematic

As a base of my circuit, I have decided on a double sided 50mm x 50mm board. This is quite big as you can see for the circuit I have made, but gives plenty of space for a soldering iron to get access. As well as this, it gives a nice amount of space for multimeter probes. I also tried to keep the individual logic chips in the same arrangement as the schematic. This is meant to be used as a learning device, so it’s useful for the chips to line up with the diagram. The header pins for the inputs and outputs are placed on opposite sides of the board to make it more obvious for the user to see it. The pins for the power and ground are on the same side on both headers. The LEDs that are directly attached to the pins are kept close to them, and the track is fairly obvious to show where the signal is from. The silkscreen labels which LED designates which input/output. All the designators have been made half the normal size due to the small amount of parts used in the project. The below images show the PCB layout I created with the top copper being red, bottom copper being blue, and the silkscreen shown in yellow.

1 bit adder 1 PCB top

As you might be able to see, I have tried to keep all the power on the bottom side of the board. This leaves lots of space for the logic signals on the top, where the user is more likely to see. As you can see, not all signals are on the top side due to circuit constraints, but signals that do swap over are generally short jump, and straight lines, This makes it more obvious where the tracks go without having to flip the board.

1 bit adder 1 PCB bottom

As noted above I used 7400 LVC series logic gates. The SOT23-5 package chips have the suffix of “BVD”. See the datasheets for each of the devices for more information. I have written a simple bill of materials below:

2x SN74LVC1G86DBVT – XOR gate
2x SN74LVC1G08DBVT – AND gate
1x SN74LVC1G32DBVT – OR gate
5x DO-214 LED’s
5x 0805 220Ω resistors
2x 5-pin 0.1″ header pins