Previously I went through the three input NOR gate that ran the Apollo Guidance Computer and how the circuit works. Previous to that I also told the story of how this chip partially funded Silicon Valley as we know it today. This post builds on that and goes through how the silicon works, and the simplicity of the circuit. Quite a famous image of the chip, fairly detailed image of the silicon inside the device spurred on this post, and taught me lots about silicon that I want to pass on.
The above schematic of the 3 input NOR gate is also shown in previous posts. It is from the NASA Apollo Guidance Computer schematic, but I have annotated it so that I can reference to specific parts. It is a handy schematic considering it was right at the start of the development of semiconductors. The first image in the post is the best image of the silicon, but is not very big. The biggest image I can find is not quite as sharp, but is much better to annotate, it is the same chip. The first annotation shows the pinout of the device, and how those pins actually connect to the pins.
The noted parts of the above images are pins 5 and 10, and are the starting points to deciphering the layout. If you look at pin 5 and 10 on the schematic, they correspond to GND and power respectively. They are the only pins that are shared between both NOR gates. Apart from that the two sides look remarkably similar, and are basically a mirrored version. To figure which is ground and which is power, the resistors need to be taken into account.
The above image shows the resistors found on the device. They tend to just be a thin section of P doped silicon, and above connect two sections of aluminum to form a resistor. It is also noted that there is big section of brown surrounding the whole circuit. Although it functions like a resistor and is made in the same way, it is puterly for ESD purposes, protecting the circuit. This big ring also is a big hint that it is connected to ground (pin 5). the second hint is that GND has no resistors attached to it on the schematic, but power has two. They are R1 and R2, connecting to pin 9 and 1 respectively, and are pull up resistors. Pin R3 to R8 are simply the base resistors for the transistors. They are all roughly the same size, and are there are 6 of them. The transistors are also fairly obvious in the centre of the silicon.
The above image is showing the heart of the device. the 6 transistors that make it resistor-transistor logic. As you can see in the above image, all the collectors are connected together, connected to pins 1 and 9. If you look closely, the base and emitter of each transistor sit inside a brown section like the resistors. This is P doped silicon and forms the base-emitter junction. This allows the base and emitter to sit anywhere within that P doped silicon detection to work. This means that the transistors do not conform to the standard Collector-base-emitter topology. All of the emitters are also connected together via the aluminium placed on the top, but the P doped sections of each device are seperate. As all the transistors of each device have common emitters, it doesn’t matter that they are all connected together, by design, only one of the transistors needs to be on for it to function.
The above image found on Ken Shirriff’s blog shows how the transistor works with the emitter and base in the P doped silicon. I may do some more posts about it, but his blog is a great place to find more information on silicon reverse engineering.
The above image is an interesting one I found while researching this chip. A section in electronics world 1963 showing how micrologic is made. The type G chip was part of the second batch of micrologic circuits. This section was useful to see how silicon was actually manufactured, and in some ways, still is today.